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NCP1217, NCP1217A
Duty Cycle Typ = 74%
2.9 V
0V
Latching Off the NCP1217
Total latched shutdown can easily be implemented
through a simple PNP bipolar transistor as depicted by
Figure 23. When OFF, Q1 is transparent to the operation.
When forward biased, the transistor pulls the Adj pin toward
+
--
L.E.B.
19 k
CS
Rcomp
V CC and permanently latches--off the IC as soon Vadj goes
above the latching level (typical 3.1 V). Figure 23 shows
how to wire the bipolar transistor to activate the latchoff. A
typical candidate for Q1 could be an MMBT3906 from
Rsense
From
Setpoint
Figure 22. Inserting a Resistor in Series with the Current
ON Semiconductor.
V CC
Sense Information Brings Ramp Compensation
In the NCP1217, the ramp features a swing of 2.9 V with
a duty cycle max at 74%. Over a 65 kHz frequency, for
instance, it corresponds to a 254 mV/ m s ramp. In our
FLYBACK design, let’s suppose that our primary
Off
Q1
Rlimit
inductance Lp is 350 m H, delivering 12 V with a Np:Ns ratio
of 1:0.1. The OFF time primary current slope is thus given
1
2
8
7
(Vout + Vf) ·
by:
= 371 mA ∕ m s or 37 mV ∕ m s when
Np
Ns
Lp
projected over an Rsense of 0.1 Ω , for instance. If we select
3
4
6
5
CV CC
75% of the downslope as the required amount of ramp
compensation, then we shall inject 27 mV/ m s. Our
internal compensation being of 254 mV/ m s, the divider
ratio ( divratio ) between Rcomp and the 19 k Ω is 0.106.
A few lines of algebra to determine Rcomp:
Figure 23. A Simple Bipolar Transistor Totally
Disables the IC
19 k · divratio
(1--divratio)
= 2.26 k Ω .
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